Analog Electronics

Diode rectifier and regulator circuits

A rectifier converts AC into pulsating DC, and a regulator holds the output voltage nearly constant despite changes in input voltage or load current. The main design quantities are the peak inverse voltage (PIV), the peak and average diode currents, the series resistor needed for Zener regulation, and the efficiency of a linear regulator.

Peak inverse voltage. In a full-wave bridge rectifier, each reverse-biased diode blocks the full peak of the input, so PIV equals V_m. A centre-tapped full-wave rectifier instead sees about 2V_m across the off diode. When the supply is specified as an RMS value with a tolerance, design for the upper limit: V_m = \sqrt{2}\,V_{rms,max}.

Average current of an ideal diode with a battery. The diode conducts only while the source voltage exceeds the battery voltage. The average current is found by integrating the conducting part of the current over one period and dividing by 2\pi (or by T), with the integration limits set by the points where v_s crosses the battery voltage.

Series inductance at line frequency. If \omega L \ll R at the supply frequency, the inductor contributes negligible impedance, so the peak current is approximately V_{pk}/R. The time constant L/R must be compared with the half period to decide whether the current follows the voltage.

Zener regulation limit. A Zener diode regulates only while its current stays nonnegative at the minimum input voltage. For series resistor R_s and load R_L, the condition is (V_{in,min}-V_Z)/R_s \ge V_Z/R_L, which gives R_L \ge V_Z R_s/(V_{in,min}-V_Z). The Zener power rating is checked separately at maximum input.

Efficiency of a linear regulator. In a series pass regulator, the input current equals the load current when bias currents are neglected. Efficiency is then \eta = P_{out}/P_{in} = V_{out}/V_{in}. For example, a 12 V input with a 5 V output gives \eta \approx 41.7\%.

BJT DC biasing

DC biasing sets the quiescent collector current and the collector-emitter voltage so that the transistor stays in the active region. The standard method reduces the base divider to a Thevenin equivalent, then applies Kirchhoff's voltage law around the base-emitter loop and the output loop.

Key relations. The base-emitter drop is taken as 0.7 V for silicon NPN, and the sign reverses for a PNP device, where V_{EB} is used. The current gains are I_C = \beta I_B, I_E = (\beta+1)I_B, and \alpha = \beta/(\beta+1). The Thevenin voltage and resistance of a base divider R_1, R_2 are V_{TH} = V_{CC}R_2/(R_1+R_2) and R_{TH} = R_1R_2/(R_1+R_2).

Base loop with emitter resistor. The input loop is V_{TH} = I_B R_{TH} + V_{BE} + (\beta+1)I_B R_E. Solving this gives I_B, then I_C, and the output loop V_{CE} = V_{CC} - I_C R_C - I_E R_E gives the Q-point. Check that V_{CE} is above the saturation value.

Zener-stabilised emitter follower. When a Zener diode holds the base node, the emitter is at V_Z - V_{BE} when the base current is small, and the load current is set by the emitter voltage across the load. A small base-resistor current gives a load current about \beta times the base current, so the load voltage stays nearly fixed as the input varies.

MOSFET small-signal amplifier configurations

A MOSFET amplifier is analysed with the small-signal model, in which the device is replaced by the transconductance g_m and the output resistance r_{ds} (or r_o), and the gate draws no current. The three basic configurations differ in which terminal receives the input and which is the output.

Common source (CS). The input is at the gate and the output is at the drain. The voltage gain is A_v = -g_m R_D, so the stage is inverting.

Common gate (CG). The gate is at signal ground, the input is at the source, and the output is at the drain. The voltage gain is +g_m R_D, so the stage is non-inverting.

Common drain (source follower). The output is at the source and follows the gate with gain close to unity. Because the ideal gate draws zero current while the output drives a load, the current gain i_o/i_{in} is infinite in the ideal model.

Output resistance of stacked devices. When two saturated transistors are stacked with a fixed gate voltage on the lower device, the output resistance seen looking into the top drain is approximately R_{out} = r_{ds1} + r_{ds2} + g_{m2}r_{ds1}r_{ds2}. For identical devices this is 2r_{ds} + g_m r_{ds}^2. The output impedance is finite because each channel has finite r_{ds}.

Op-amp feedback configurations

Negative feedback makes the two input terminals of an ideal op-amp equal in potential (V_+ = V_-) and draws no input current. These two rules solve most feedback circuits.

Voltage follower (buffer). When the output is connected directly to the inverting input, the output equals the non-inverting input voltage with unity gain. The input draws no current, so the buffer isolates a source from a load.

Non-inverting stage and cascades. For a non-inverting amplifier with feedback resistor R_f and ground resistor R_1, the gain is 1 + R_f/R_1. When two stages are cascaded, multiply the gains, but first check whether a later stage loads the earlier one, since the rules V_+ = V_- and zero input current still apply node by node.

Closed-loop gain with finite open-loop gain. With open-loop gain A_0 and feedback factor \beta, the closed-loop gain is A_{cl} = A_0/(1 + A_0\beta). For an inverting amplifier with \beta = R_1/(R_1+R_f), the ideal gain -R_f/R_1 is reduced in magnitude by the factor 1/(1 + (1+R_f/R_1)/A_0), where 1+R_f/R_1 is the noise gain.