Semiconductor Devices

MOS capacitor inversion charge and threshold voltage

In a MOS capacitor on a p-type substrate, strong inversion begins when the surface electron density equals the bulk hole density, and the threshold voltage V_T is the gate voltage at which this happens. Above threshold, the inversion charge per unit area is set by the gate overdrive, Q_{IN}=C_{ox}(V_G-V_T), where C_{ox}=\varepsilon_{ox}/t_{ox}. Because V_T is fixed for a given device, a change in gate voltage in strong inversion changes the inversion charge by exactly C_{ox}\,\Delta V_G, so you can find the new charge from the old one without recalculating V_T. Do not confuse this with the depletion charge, which stays nearly constant once inversion starts. Example: if C_{ox}=2\,\mu\text{F/cm}^2 and V_G rises by 1 V in strong inversion, Q_{IN} increases by 2\,\mu\text{C/cm}^2.

Threshold voltage is tied to flatband voltage, which is set by the metal-semiconductor work-function difference and the fixed oxide charge. The flatband voltage is V_{FB}=\phi_{ms}-Q_f/C_{ox} with \phi_{ms}=\phi_m-\phi_s, so a positive fixed oxide charge Q_f lowers V_{FB}, and setting V_{FB}=0 lets you back-calculate the semiconductor work function from the metal work function and Q_f/C_{ox}. Example: with \phi_m=4.8 eV, Q_f/C_{ox}=0.2 V, and V_{FB}=0, the semiconductor work function is \phi_s=4.6 eV.

MOSFET body effect and substrate sensitivity

The body effect occurs when the source is at a potential different from the substrate. Reverse biasing the source-body junction widens the depletion region, which raises the threshold voltage: V_T=V_{T0}+\gamma\left(\sqrt{2\phi_F+|V_{SB}|}-\sqrt{2\phi_F}\right). The body coefficient is \gamma=\sqrt{2q\varepsilon_{Si}N_A}/C_{ox}, so it depends on the substrate doping N_A and the oxide capacitance.

The substrate sensitivity is the slope \partial V_T/\partial|V_{SB}|=\gamma/\left(2\sqrt{2\phi_F+|V_{SB}|}\right). When |V_{SB}|\gg 2\phi_F, this reduces to \gamma/(2\sqrt{|V_{SB}|}). Because it is a slope, it is given in V/V, and it falls as the bias grows. If the sensitivity, the oxide thickness, and the bias are known, you can recover \gamma and then the doping N_A, which is the usual exam route. Example: with \gamma=0.4\ \text{V}^{1/2} and |V_{SB}|=4 V, the sensitivity is 0.4/(2\times 2)=0.1 V/V.

PN junction built-in voltage and depletion width

The built-in voltage of an abrupt PN junction is V_{bi}=\frac{kT}{q}\ln\left(\frac{N_AN_D}{n_i^2}\right), which is the potential barrier at zero bias. Under reverse bias V_R, the total depletion width is W=x_n+x_p, where the charge-neutrality condition N_Ax_p=N_Dx_n holds. The depletion width on each side is x_n=\sqrt{\dfrac{2\varepsilon_s(V_{bi}+V_R)}{q}\dfrac{N_A}{N_D(N_A+N_D)}}, with the analogous expression for x_p.

The depletion region extends more into the more lightly doped side, so the lightly doped side has the wider depletion region. When the reverse bias is increased, the junction depletes one side completely before the other, and that side is the one whose physical width is reached first. To decide which side depletes first, compute the depletion width each side would need and compare it with that side's physical thickness. Example: if N_A=10N_D and the P side is physically thicker than the N side, the N side depletes first, because x_p=x_n N_D/N_A is then the smaller width.

CMOS inverter voltage transfer characteristic

The voltage transfer characteristic (VTC) of a CMOS inverter gives the output voltage as a function of the input voltage. It has distinct regions: the output is high while the nMOS is off, falls sharply near the switching threshold where both devices are in saturation, and is low when the pMOS is off. The switching threshold is where the two saturation currents are equal, and its position depends on the ratio of mobility times W/L of the two devices.

When a steady-state output node is tied to the gate of both transistors, each device becomes diode-connected, and the output settles at the voltage where the pMOS and nMOS saturation currents balance: \tfrac12\mu_pC_{ox}(W/L)_p(V_{SG}-|V_{tp}|)^2=\tfrac12\mu_nC_{ox}(W/L)_n(V_{GS}-V_{tn})^2. The stronger device, meaning larger \mu\,W/L, pulls the output toward its rail. Each device must also satisfy the saturation condition V_{DS}\ge V_{GS}-V_t for this balance to hold. Example: if the pMOS has (W/L)_p=2, the nMOS has (W/L)_n=1, and \mu_p=\mu_n/2, then the two currents are equal when the overdrive ratio satisfies (V_{SG}-|V_{tp}|)^2/(V_{GS}-V_{tn})^2=1/(2\times 0.5)=1.

MOSFET operating regions and threshold voltage

An NMOS device is in cutoff when V_{GS}<V_t, in the linear (triode) region when V_{DS}<V_{GS}-V_t, and in saturation when V_{DS}\ge V_{GS}-V_t. For a PMOS, the same conditions apply with the signs reversed, using V_{SG}, V_{SD}, and |V_{tp}|. The overdrive V_{ov}=V_{GS}-V_t is the key quantity that separates the regions.

A useful application is the pass-transistor limit. When an NMOS with its gate and drain both at V_{DD} charges a capacitor connected to its source, the source voltage rises until V_{GS} falls to V_t, so the output stops at V_{DD}-V_t. A PMOS can pull its output up to its source potential, because its V_{SG} stays above |V_{tp}| as long as the gate is low enough. Example: if V_{DD}=5 V and V_t=1 V, an NMOS pass transistor with its gate at 5 V charges a node only to 4 V.

Semiconductor device operating principles

An intrinsic semiconductor at thermal equilibrium has equal electron and hole densities, n=p=n_i, because each thermally generated electron leaves behind a hole. Doping breaks this equality, so np=n_i^2 holds for both intrinsic and doped material at equilibrium, but n=p holds only for intrinsic material.

In steady state, the total current density, consisting of the conduction current and the displacement current, has zero divergence. This means the total current is spatially constant through any two-terminal device in steady state, even though the electron and hole components can vary along the device. In a BJT, the base is lightly doped relative to the emitter, and the collector is normally more lightly doped than the base, so the collector is not more heavily doped. Electron mobility in silicon decreases with temperature above about 300 K because lattice (phonon) scattering dominates, roughly as \mu\propto T^{-2.4}. Avoid assuming that mobility rises with temperature in this range.

MOS capacitor depletion width versus gate voltage

The depletion width of a MOS capacitor on a p-type substrate depends on the gate voltage through three regimes. In accumulation, V_g<V_{fb}, majority carriers collect at the surface, so no depletion region exists and W_{dep}=0. Between V_{fb} and V_t, the surface is depleted and the depletion width grows with gate voltage as W_{dep}=\sqrt{2\varepsilon_s\psi_s/(qN_A)}, where \psi_s is the surface potential.