Analog and Digital Electronics

Op-amp circuit analysis

An ideal operational amplifier has infinite open-loop gain, infinite input impedance and zero output impedance. In linear operation with negative feedback, two rules follow: the voltage between the input terminals is zero (the virtual short, v_+ = v_-), and no current enters either input terminal. Analysis applies these rules together with nodal equations written at the inverting and non-inverting nodes, and the solved output must then be checked against the supply rails. If the solution exceeds the rails, the amplifier saturates and the output is clamped at the rail voltage, so the linear assumption was wrong.

In a voltage follower the output is fed directly back to the inverting input, so the feedback factor is unity, the differential input is zero and V_{out} = V_{in}. An inverting summing amplifier with its non-inverting input grounded has V_{out} = -R_f \sum_i (V_i / R_i), because the inverting node is a virtual ground.

Positive feedback changes the behaviour completely. When the output is fed to the non-inverting input and the inverting terminal is grounded, the output is driven to one of two saturation levels, +V_{sat} or -V_{sat}, and both states are stable. Such a circuit is bistable, not oscillating. A circuit with no reactive element or time-varying feedback cannot be astable.

When a capacitance changes with time, the current through it is i = v\,dC/dt, which differs from the usual C\,dv/dt relation. In an op-amp circuit with a virtual ground, this current flows entirely through the feedback resistor, so the output equals v_0 = -iR.

The input impedance of an op-amp stage is not always infinite. When the feedback network draws current from the source through the inverting node, the input impedance is finite and can even be negative. It is computed as Z_{in} = V_{in}/I_{in}, with I_{in} found from the complete network.

An all-pass filter has unit magnitude at every frequency. This requires the numerator polynomial of the transfer function to be the mirror image of the denominator, so that the zeros are the reflections of the poles across the imaginary axis. Matching coefficients of the two polynomials then gives the design condition on the resistor values.

ADC and DAC quantization

An N-bit uniform quantizer has a quantization error distributed uniformly over one LSB. For a full-scale sinusoidal input, the peak signal-to-quantization-noise ratio is \text{SQNR} = 6.02N + 1.76 dB. Each bit removed lowers this ratio by about 6 dB, so a signal that passes through fewer effective bits carries more noise.

An n-bit successive approximation ADC needs one clock cycle for the start-of-conversion signal, n cycles for the bit trials and one cycle for the end-of-conversion signal, which gives n+2 cycles in total. The maximum sampling rate is the reciprocal of this conversion time. By the Nyquist criterion, the highest input frequency that can be sampled without aliasing is half the sampling rate, f_s/2.

For an ideal n-bit DAC with full-scale voltage V_{FS}, the output for code N is V_{out} = V_{FS}\,N/(2^n - 1). The output is 0 V at code zero and V_{FS} at the all-ones code, so the step size is V_{FS}/(2^n-1). The conversion is linear in the code, and a common error is to divide by 2^n instead of 2^n - 1.

MOSFET small-signal model

In saturation, the square-law drain current gives a transconductance g_m = \mu_n C_{ox}(W/L)V_{OV}, where V_{OV} = V_{GS} - V_{th}. Channel-length modulation is neglected when the problem says so. The body effect adds a second transconductance, g_{mb}, which is often expressed as a ratio \eta = g_{mb}/g_m. A signal applied to the bulk changes the drain current through g_{mb}v_{bs}. When the gate is held at a fixed voltage, the bulk path is therefore the only signal path, and the gain depends on g_{mb} rather than on g_m.

In saturation the parasitic capacitances follow a fixed order. The gate-source capacitance C_{GS} includes the intrinsic channel term \frac{2}{3}WLC_{ox} together with overlap, so it is the largest. The gate-drain capacitance C_{GD} contains only the overlap capacitance, because the channel is pinched off at the drain. The drain-source capacitance C_{DS} is a reverse-biased junction capacitance and is usually the smallest. The resulting order is C_{GS} > C_{GD} > C_{DS}.

Combinational logic circuit analysis

To analyze a combinational circuit, write the Boolean expression at each gate output, substitute the intermediate signals successively and tabulate the result over all input combinations. Blocks such as the half adder are common building units, in which the sum output is an XOR and the carry output is an AND. For a multi-output circuit, the maximum output value is found by checking which output patterns actually occur, because some combinations of intermediate signals never happen.

A sum bit is the XOR X \oplus Y = \bar{X}Y + X\bar{Y}, which is 1 only when the two inputs differ. In a decoder-style sum-of-products realization, each minterm is picked out by an AND gate and combined by an OR gate. A data input connected to 1 passes its minterm, and a data input connected to 0 removes it, so the constant inputs select exactly the minterms that make the function true.

Logic gate propagation delay

Each gate output changes only after its input-to-output propagation delay. When a signal reaches the output by two paths with different delays, the output pulse appears between the arrival times of the two transitions, and its width is the difference between those times. Trace each edge through the delays of the gates on its path, and then compare the arrival times.

In a circuit with NAND gates and an inverter, the high and low durations of the output are found separately from the sum of gate delays along each edge path. The duty cycle equals the high time divided by the period, multiplied by 100 percent. Tracking each transition in order, rather than estimating the waveform, avoids mistakes when the delays differ between gates.